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» Formal testing from timed finite state machines
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GLVLSI
2007
IEEE
151views VLSI» more  GLVLSI 2007»
13 years 11 months ago
Hand-in-hand verification of high-level synthesis
This paper describes a formal verification methodology of highnthesis (HLS) process. The abstraction level of the input to HLS is so high compared to that of the output that the v...
Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Ma...
KBSE
2000
IEEE
13 years 12 months ago
Model Checking Programs
The majority of work carried out in the formal methods community throughout the last three decades has (for good reasons) been devoted to special languages designed to make it eas...
Willem Visser, Klaus Havelund, Guillaume P. Brat, ...
FATES
2004
Springer
14 years 28 days ago
Online Testing of Real-time Systems Using Uppaal
We present the development of T-UPPAAL — a new tool for online black-box testing of real-time embedded systems from non-deterministic timed automata specifications. It is based ...
Kim Guldstrand Larsen, Marius Mikucionis, Brian Ni...
RV
2010
Springer
220views Hardware» more  RV 2010»
13 years 5 months ago
Runtime Verification with the RV System
The RV system is the first system to merge the benefits of Runtime Monitoring with Predictive Analysis. The Runtime Monitoring portion of RV is based on the successful Monitoring O...
Patrick O'Neil Meredith, Grigore Rosu
SIGMETRICS
2002
ACM
107views Hardware» more  SIGMETRICS 2002»
13 years 7 months ago
Passage time distributions in large Markov chains
Probability distributions of response times are important in the design and analysis of transaction processing systems and computercommunication systems. We present a general tech...
Peter G. Harrison, William J. Knottenbelt