164 search results - page 2 / 33 » Formal testing from timed finite state machines |
DSD
2002
IEEE
14 years 13 days ago
2002
IEEE
We use a formal tool to extract Finite State Machines (FSM) based representations (lists of states and transitions) of sequential circuits described by flip-flops and gates. The...
APSEC
2009
IEEE
13 years 5 months ago
2009
IEEE
Abstract--Formal methods are very useful in software industry and are becoming of paramount importance in practical engineering techniques. They involve the design and the modeling...
SEC
2003
13 years 8 months ago
2003
Abstract This paper presents a systematic approach to developing Java Card applets and/or formal specifications for them, starting from descriptions in the form of finite state m...
ICST
2009
IEEE
14 years 2 months ago
2009
IEEE
The problem of testing from an extended finite state machine (EFSM) can be expressed in terms of finding suitable paths through the EFSM and then deriving test data to follow the ...
COMCOM
1999
13 years 7 months ago
1999
If a test does not produce the expected output, the incorrect output may have been caused by an earlier state transfer failure. Ghedamsi and von Bochmann [1992] and Ghedamsi et al...