299 search results - page 10 / 60 » Formal verification of analog designs using MetiTarski |
DAC
2009
ACM
14 years 8 months ago
2009
ACM
Continuously shrinking feature sizes result in an increasing susceptibility of circuits to transient faults, e.g. due to environmental radiation. Approaches to implement fault tol...
SBMF
2010
Springer
13 years 2 months ago
2010
Springer
Designers of concurrent and distributed algorithms usually express them using pseudo-code. In contrast, most verification techniques are based on more mathematically-oriented forma...
SECURWARE
2007
IEEE
14 years 1 months ago
2007
IEEE
The paper discusses an experience in using a realtime UML/SysML profile and a formal verification toolkit to check a secure group communication system against temporal requirement...
ATVA
2009
Springer
13 years 11 months ago
2009
Springer
We present a framework for certifying hardware designs generated through behavioral synthesis, by using formal verification to certify the associated synthesis transformations. We ...
MTV
2007
IEEE
14 years 1 months ago
2007
IEEE
Abstract—Abstract models of analog/mixed-signal (AMS) circuits can be used for formal verification and system-level simulation. The difficulty of creating these models preclude...