299 search results - page 19 / 60 » Formal verification of analog designs using MetiTarski |
APSEC
2008
IEEE
13 years 9 months ago
2008
IEEE
Formal verification of Function Block Diagram (FBD) based software is an essential task when replacing traditional relay-based analog system with PLC-based software in nuclear rea...
ICST
2009
IEEE
13 years 5 months ago
2009
IEEE
A software development process is conceptually an abstract form of model transformation, starting from an enduser model of requirements, through to a system model for which code c...
FMAM
2010
13 years 5 months ago
2010
: In this paper, we present the experience gained with the participation in a case study in which a novel high-level design language (UML4SOA) was used to produce a service-oriente...
MEMOCODE
2010
IEEE
13 years 5 months ago
2010
IEEE
Electronic System Level (ESL) design manages the complexity of todays systems by using abstract models. In this context Transaction Level Modeling (TLM) is state-of-theart for desc...
ACSW
2006
13 years 8 months ago
2006
Formal specification and verification of protocols have been credited for uncovering protocol flaws; revealing inadequacies in protocol design of the Initial Stage and Negotiation...