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» Formal verification of analog designs using MetiTarski
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AGTIVE
2007
Springer
13 years 11 months ago
Transforming Timeline Specifications into Automata for Runtime Monitoring
Abstract. In runtime monitoring, a programmer specifies code to execute whenever a sequence of events occurs during program execution. Previous and related work has shown that runt...
Eric Bodden, Hans Vangheluwe
WWW
2005
ACM
14 years 8 months ago
Web service interfaces
We present a language for specifying web service interfaces. A web service interface puts three kinds of constraints on the users of the service. First, the interface specifies th...
Dirk Beyer, Arindam Chakrabarti, Thomas A. Henzing...
POPL
2010
ACM
14 years 4 months ago
Contracts Made Manifest
Since Findler and Felleisen [2002] introduced higher-order contracts, many variants have been proposed. Broadly, these fall into two groups: some follow Findler and Felleisen in u...
Benjamin C. Pierce, Michael Greenberg, Stephanie W...
IFIP
2001
Springer
13 years 12 months ago
Functional Test Generation using Constraint Logic Programming
— Semi-formal verification based on symbolic simulation offers a good compromise between formal model checking and numerical simulation. The generation of functional test vector...
Zhihong Zeng, Maciej J. Ciesielski, Bruno Rouzeyre
CASES
2006
ACM
14 years 1 months ago
Modeling heterogeneous SoCs with SystemC: a digital/MEMS case study
Designers of SoCs with non-digital components, such as analog or MEMS devices, can currently use high-level system design languages, such as SystemC, to model only the digital par...
Ankush Varma, Muhammad Yaqub Afridi, Akin Akturk, ...