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» Formal verification of analog designs using MetiTarski
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B
2007
Springer
13 years 11 months ago
Automatic Translation from Combined B and CSP Specification to Java Programs
Abstract. A recent contribution to the formal specification and verification of concurrent systems is the integration of the state- and event-based approaches B and CSP, specifical...
Letu Yang, Michael Poppleton
FMCAD
2006
Springer
13 years 11 months ago
Ario: A Linear Integer Arithmetic Logic Solver
Ario is a solver for systems of linear integer arithmetic logic. Such systems are commonly used in design verification applications and are classified under Satisfiability Modulo T...
Hossein M. Sheini, Karem A. Sakallah
FORMATS
2010
Springer
13 years 5 months ago
Layered Composition for Timed Automata
Abstract. We investigate layered composition for real-time systems modelled as (networks of) timed automata (TA). We first formulate the principles of layering and transition indep...
Ernst-Rüdiger Olderog, Mani Swaminathan
TCBB
2008
137views more  TCBB 2008»
13 years 7 months ago
Toward Verified Biological Models
The last several decades have witnessed a vast accumulation of biological data and data analysis. Many of these data sets represent only a small fraction of the system's behav...
Avital Sadot, Jasmin Fisher, Dan Barak, Yishai Adm...
FPGA
2009
ACM
200views FPGA» more  FPGA 2009»
14 years 2 months ago
FPGA-based front-end electronics for positron emission tomography
Modern Field Programmable Gate Arrays (FPGAs) are capable of performing complex discrete signal processing algorithms with clock rates above 100MHz. This combined with FPGA’s lo...
Michael Haselman, Robert Miyaoka, Thomas K. Lewell...