97 search results - page 12 / 20 » Formal verification of behavioral VHDL specifications: a cas... |
HICSS
2003
IEEE
14 years 3 months ago
2003
IEEE
The paper reports on an analysis technology based on the tracing approach to test trustworthy requirements of a distributed system. The system under test is instrumented such that...
APSEC
2008
IEEE
14 years 12 days ago
2008
IEEE
Formal verification of Function Block Diagram (FBD) based software is an essential task when replacing traditional relay-based analog system with PLC-based software in nuclear rea...
FAC
2000
13 years 10 months ago
2000
Formal approaches to the design of interactive systems rely on reasoning about properties of the t a very high level of abstraction. Specifications to support such an approach typi...
ATAL
2010
Springer
13 years 11 months ago
2010
Springer
Information security is vital to many multiagent system applications. In this paper we formalise the notion of detectability of attacks in a MAS setting and analyse its applicabil...
ENTCS
2008
13 years 10 months ago
2008
We present the current state of our STSLib project. This project aims at defining an environment to formally specify and execute software components. One important feature is that...