97 search results - page 6 / 20 » Formal verification of behavioral VHDL specifications: a cas... |
AICCSA
2001
IEEE
14 years 2 months ago
2001
IEEE
This paper2 details the stages of building a substantial, carefully specified, fully tested and fully operational university and school timetabling system. This is reported as a c...
SPIN
2000
Springer
14 years 1 months ago
2000
Springer
The Temporal Rover is a specification based verification tool for applications written in C, C++, Java, Verilog and VHDL. The tool combines formal specification, using Linear-Time ...
JUCS
2010
13 years 5 months ago
2010
Abstract: Model-Driven Architecture (MDA) presents a set of layered models to separate design concerns from platform concerns. The model executability for each model element is sti...
COMPSAC
2007
IEEE
14 years 2 months ago
2007
IEEE
Hardware/software co-verification is becoming an indispensable tool for building highly trustworthy embedded systems. A stumbling block to effective co-verification using model ch...
ICSE
2008
IEEE-ACM
14 years 11 months ago
2008
IEEE-ACM
We report on the successful application of academic experience with formal modelling and verification techniques to an automotive scenario from the service-oriented computing doma...