97 search results - page 7 / 20 » Formal verification of behavioral VHDL specifications: a cas... |
ISCAS
2003
IEEE
14 years 3 months ago
2003
IEEE
To handle today’s complexity, modern circuits and systems be specified at a high level of abstraction. Recently, SystemC has been proposed as a language that allows a fast on o...
ATAL
2006
Springer
14 years 2 months ago
2006
Springer
Comprehending and analyzing agent behavior is an arduous task due to complexities in agent systems and sophistication of agent behaviors, in addition to the common difficulties wi...
CAI
2006
Springer
13 years 10 months ago
2006
Springer
In this paper, formal verification methodologies and the SPR (Safety Problem Resolver) model checking tool are used for verifying a security model's safety. The SPR tool makes...
HYBRID
2007
Springer
14 years 2 months ago
2007
Springer
Abstract. In this paper, we propose a new approach for formal verification of hybrid systems. To do so, we present a new refinement proof technique, a weak refinement using step in...
IWFM
1998
13 years 11 months ago
1998
In this paper, we present a proof that the bitonic sort is sound using PVS, a powerful specification and verification environment. First, we briefly introduce this well-known para...