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ISQED
2003
IEEE
113views Hardware» more  ISQED 2003»
14 years 19 days ago
Using Integer Equations for High Level Formal Verification Property Checking
This paper describes the use of integer equations for high level modeling digital circuits for application of formal verification properties at this level. Most formal verificatio...
Bijan Alizadeh, Mohammad Reza Kakoee
SIGSOFT
2007
ACM
14 years 8 months ago
The symmetry of the past and of the future: bi-infinite time in the verification of temporal properties
Model checking techniques have traditionally dealt with temporal logic languages and automata interpreted over -words, i.e., infinite in the future but finite in the past. However...
Matteo Pradella, Angelo Morzenti, Pierluigi San Pi...
FDL
2005
IEEE
14 years 29 days ago
Formal Evaluation of Quality of Service for Data Acquisition
In the field of real-time control applications, validation relies on a precise knowledge of the temporal characteristics of the used data such as delays and loss rates. These data...
Hedia B. Ben, F. Jumel, Jean-Philippe Babau
FDL
2007
IEEE
13 years 11 months ago
Towards Assertion Based Verification of Analog and Mixed Signal Designs Using PSL
Abstract-- Analog and Mixed Signal (AMS) designs are important integrated systems that link digital circuits to the analog world. Following the success of PSL verification methodol...
Ghiath Al Sammane, Mohamed H. Zaki, Zhi Jie Dong, ...
ICSE
1999
IEEE-ACM
13 years 11 months ago
A Practical Method for Verifying Event-Driven Software
Formal verification methods are used only sparingly in software development. The most successful methods to date are based on the use of model checking tools. To use such he user ...
Gerard J. Holzmann, Margaret H. Smith