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» Formally Specifying and Verifying Real-Time Systems
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RSP
1999
IEEE
13 years 11 months ago
System Design Validation Using Formal Models
Formal methods are a nice idea, but the size and complexity of real systems means that they are impractical. We propose that a reasonable alternative to attempting to specify and ...
Peter Henderson, Robert John Walters
FDL
2007
IEEE
13 years 11 months ago
Transactor-based Formal Verification of Real-time Embedded Systems
With the increasing complexity of today's embedded systems, there is a need to formally verify such designs at mixed abstraction levels. This is needed if some compoe describ...
Daniel Karlsson, Petru Eles, Zebo Peng
HYBRID
1992
Springer
13 years 11 months ago
A Formal Approach to Computer Systems Requirements Documentation
This paper demonstrates how the extended duration calculus [4] can be used to support the approach to documentation of computer systems presented by in [1]. This approach uses the ...
Marcin Engel, Marcin Kubica, Jan Madey, David Lorg...
EUROMICRO
2000
IEEE
13 years 12 months ago
Formal Coverification of Embedded Systems Using Model Checking
The complexity of embedded systems is increasing rapidly. In consequence, new verification techniques that overcome the limitations of traditional methods and are suitable for har...
Luis Alejandro Cortés, Petru Eles, Zebo Pen...
JANCL
2006
74views more  JANCL 2006»
13 years 7 months ago
Linear-time temporal logics with Presburger constraints: an overview
We present an overview of linear-time temporal logics with Presburger constraints whose models are sequences of tuples of integers. Such formal specification languages are welldesi...
Stéphane Demri