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» Formally Specifying and Verifying Real-Time Systems
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EPK
2006
114views Management» more  EPK 2006»
13 years 9 months ago
Verifying Properties of (Timed) Event Driven Process Chains by Transformation to Hybrid Automata
Abstract: Event-driven Process Chains (EPCs) are a commonly used modelling technique for design and documentation of business processes. Although EPCs have an easy-to-understand no...
Stefan Denne
MASCOTS
2003
13 years 9 months ago
Software Performance Modeling Using UML and Petri Nets
Abstract. Software systems are today one of the most complex artifacts, they are simultaneously used by hundred-thousand of people sometimes in risk real time operations, such as a...
José Merseguer, Javier Campos
CORR
2010
Springer
176views Education» more  CORR 2010»
13 years 7 months ago
Bus Protocols: MSC-Based Specifications and Translation into Program of Verification Tool for Formal Verification
Message Sequence Charts (MSCs) are an appealing visual formalism mainly used in the early stages of system design to capture the system requirements. However, if we move towards a...
Kamrul Hasan Talukder
IJCSA
2006
95views more  IJCSA 2006»
13 years 7 months ago
Modeling and Formal Verification of DHCP Using SPIN
The Dynamic Host Configuration Protocol (DHCP) is a widely used communication protocol. In this paper, a portion of the protocol is chosen for modeling and verification, namely th...
Syed M. S. Islam, Mohammed H. Sqalli, Sohel Khan
FM
1998
Springer
153views Formal Methods» more  FM 1998»
13 years 11 months ago
VSE: Controlling the Complexity in Formal Software Developments
We give an overview of the enhanced VSE system which is a tool to formally specify and verify systems. It provides means for structuring speci cations and it supports the developme...
Dieter Hutter, Heiko Mantel, Georg Rock, Werner St...