11 search results - page 2 / 3 » Gate Level Fault Diagnosis in Scan-Based BIST |
CSREAESA
2009
13 years 8 months ago
2009
Two embedded processor based fault injection case studies are presented which are applicable to Field Programmable Gate Arrays (FPGAs) and FPGA cores in configurable System-on-Chip...
ITC
1995
IEEE
13 years 11 months ago
1995
IEEE
A nalog circuit implementations of fuzzy logic are characterized by performing logical connectives of analog signals. They can be considered as generalization of digital circuits ...
IEAAIE
1999
Springer
13 years 11 months ago
1999
Springer
This paper introduces a new approach in the debugging of hardware designs. The design is given as a VHDL program and converted in a component connection model. The conversion is si...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
— With increasing process fluctuations in nano-scale technology, testing for delay faults is becoming essential in manufacturing test to complement stuck-at-fault testing. Desig...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
Extreme transistor scaling trends in silicon technology are soon to reach a point where manufactured systems will suffer from limited device reliability and severely reduced life...