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» Gate Sizing Using a Statistical Delay Model
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ISCAS
2008
IEEE
112views Hardware» more  ISCAS 2008»
14 years 3 months ago
Glitch-aware output switching activity from word-level statistics
— This paper presents models for estimating the transition activity of signals at the output of adders in Field Programmable Gate Arrays (FPGAs), given only word-level measures o...
Jonathan A. Clarke, George A. Constantinides, Pete...
VTC
2007
IEEE
103views Communications» more  VTC 2007»
14 years 3 months ago
On the Problems of Symbol-Spaced Tapped-Delay-Line Models for WSSUS Channels
—This paper reviews the pertinence and statistical behavior of symbol-spaced tapped-delay-line (TDL) models which are widely used to model wide-sense stationary uncorrelated scat...
Carlos A. Gutiérrez-Díaz-de-Le&oacut...
VLDB
2007
ACM
122views Database» more  VLDB 2007»
14 years 9 months ago
MIST: Distributed Indexing and Querying in Sensor Networks using Statistical Models
The modeling of high level semantic events from low level sensor signals is important in order to understand distributed phenomena. For such content-modeling purposes, transformat...
Arnab Bhattacharya, Anand Meka, Ambuj K. Singh
COMCOM
2004
145views more  COMCOM 2004»
13 years 8 months ago
Framework based on stochastic L-Systems for modeling IP traffic with multifractal behavior
In a previous work we have introduced a multifractal traffic model based on so-called stochastic L-Systems, which were introduced by biologist A. Lindenmayer as a method to model ...
Paulo Salvador, António Nogueira, Rui T. Va...
COMCOM
2007
86views more  COMCOM 2007»
13 years 9 months ago
Proxy location for minimizing delivery delay in HRM networks
In hierarchical reliable multicast schemes, the number of repair proxies and their locations influence the delivery delay. Low delivery delay is essential for the transmission of...
Sang-Seon Byun, Chuck Yoo