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» Gate Sizing Using a Statistical Delay Model
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AHS
2006
IEEE
133views Hardware» more  AHS 2006»
14 years 4 months ago
Gate-level Morphogenetic Evolvable Hardware for Scalability and Adaptation on FPGAs
Traditional approaches to evolvable hardware (EHW), in which the field programmable gate array (FPGA) configuration is directly encoded, have not scaled well with increasing cir...
Justin Lee, Joaquin Sitte
NIPS
2008
13 years 11 months ago
Accelerating Bayesian Inference over Nonlinear Differential Equations with Gaussian Processes
Identification and comparison of nonlinear dynamical system models using noisy and sparse experimental data is a vital task in many fields, however current methods are computation...
Ben Calderhead, Mark Girolami, Neil D. Lawrence
TCC
2009
Springer
184views Cryptology» more  TCC 2009»
14 years 10 months ago
Secure Arithmetic Computation with No Honest Majority
We study the complexity of securely evaluating arithmetic circuits over finite rings. This question is motivated by natural secure computation tasks. Focusing mainly on the case o...
Yuval Ishai, Manoj Prabhakaran, Amit Sahai
DIS
2007
Springer
14 years 4 months ago
Fast NML Computation for Naive Bayes Models
Abstract. The Minimum Description Length (MDL) is an informationtheoretic principle that can be used for model selection and other statistical inference tasks. One way to implement...
Tommi Mononen, Petri Myllymäki
SPAA
2005
ACM
14 years 3 months ago
Parallelizing time with polynomial circuits
We study the problem of asymptotically reducing the runtime of serial computations with circuits of polynomial size. We give an algorithmic size-depth tradeoff for parallelizing ...
Ryan Williams