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» Gate Sizing Using a Statistical Delay Model
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ASAP
2008
IEEE
167views Hardware» more  ASAP 2008»
14 years 4 months ago
Extending the SIMPPL SoC architectural framework to support application-specific architectures on multi-FPGA platforms
Process technology has reduced in size such that it is possible to implement complete applicationspecific architectures as Systems-on-Chip (SoCs) using both Application-Specific I...
David Dickin, Lesley Shannon
ISPD
2005
ACM
239views Hardware» more  ISPD 2005»
14 years 3 months ago
Mapping algorithm for large-scale field programmable analog array
Modern advances in reconfigurable analog technologies are allowing field-programmable analog arrays (FPAAs) to dramatically grow in size, flexibility, and usefulness. With thes...
I. Faik Baskaya, Sasank Reddy, Sung Kyu Lim, Tyson...
SCALESPACE
2007
Springer
14 years 4 months ago
Non-negative Sparse Modeling of Textures
This paper presents a statistical model for textures that uses a non-negative decomposition on a set of local atoms learned from an exemplar. This model is described by the varianc...
Gabriel Peyré
PAMI
2002
101views more  PAMI 2002»
13 years 10 months ago
On the Dependence of Handwritten Word Recognizers on Lexicons
The performance of any word recognizer depends on the lexicon presented. Usually large lexicons or lexicons containing similar entries pose greater difficulty for recognizers. How...
Hanhong Xue, Venu Govindaraju
COMCOM
1999
122views more  COMCOM 1999»
13 years 10 months ago
An accurate performance model of shared buffer ATM switches under hot spot traffic
Asynchronous transfer mode (ATM) switches based on shared buffering are known to have better performance and buffer utilization than input or output queued switches. Shared buffer...
Mahmoud Saleh, Mohammed Atiquzzaman