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MICRO
2000
IEEE
68views Hardware» more  MICRO 2000»
13 years 12 months ago
Performance improvement with circuit-level speculation
Current superscalar microprocessors’ performance depends on its frequency and the number of useful instructions that can be processed per cycle (IPC). In this paper we propose a...
Tong Liu, Shih-Lien Lu
VLSID
2003
IEEE
114views VLSI» more  VLSID 2003»
14 years 8 months ago
Substrate Bias Effect on Cycling Induced Performance Degradation of Flash EEPROMs
Cycling induced performance degradation of flash EEPROMs has been reported for VB=0 and VB<0 programming operation. Compared to VB=0, VB<0 programming shows lower interface ...
S. Mahapatra, S. Shukuri, Jeff Bude
FPGA
2000
ACM
128views FPGA» more  FPGA 2000»
13 years 11 months ago
Factoring large numbers with programmable hardware
The fastest known algorithms for factoring large numbers share a core sieving technique. The sieving cores find numbers that are completely factored over a prime base set raised t...
Hea Joung Kim, William H. Mangione-Smith
GLVLSI
2000
IEEE
145views VLSI» more  GLVLSI 2000»
13 years 12 months ago
CMOS system-on-a-chip voltage scaling beyond 50nm
† The limits on CMOS energy dissipation imposed by subthreshold leakage currents and by wiring capacitance are investigated for CMOS generations beyond 50nm at NTRS projected loc...
Azeez J. Bhavnagarwala, Blanca Austin, Ashok Kapoo...
ICCD
2006
IEEE
95views Hardware» more  ICCD 2006»
14 years 4 months ago
Scale in Chip Interconnect requires Network Technology
— Continued scaling of CMOS has lead to a problem of scale as gates are faster than light travelling across a chip. Scalability used to be the hallmark of CMOS. Half the size, do...
Enno Wein