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FPGA
2008
ACM
174views FPGA» more  FPGA 2008»
13 years 9 months ago
Pattern-based behavior synthesis for FPGA resource reduction
Pattern-based synthesis has drawn wide interest from researchers who tried to utilize the regularity in applications for design optimizations. In this paper we present a general p...
Jason Cong, Wei Jiang
PASTE
2010
ACM
14 years 22 days ago
Opportunities for concurrent dynamic analysis with explicit inter-core communication
Multicore is now the dominant processor trend, and the number of cores is rapidly increasing. The paradigm shift to multicore forces the redesign of the software stack, which incl...
Jungwoo Ha, Stephen P. Crago
IEEEPACT
2003
IEEE
14 years 28 days ago
Picking Statistically Valid and Early Simulation Points
Modern architecture research relies heavily on detailed pipeline simulation. Simulating the full execution of an industry standard benchmark can take weeks to months to complete. ...
Erez Perelman, Greg Hamerly, Brad Calder
IPPS
2009
IEEE
14 years 2 months ago
Annotation-based empirical performance tuning using Orio
In many scientific applications, significant time is spent tuning codes for a particular highperformance architecture. Tuning approaches range from the relatively nonintrusive (...
Albert Hartono, Boyana Norris, Ponnuswamy Sadayapp...
ICMCS
2007
IEEE
144views Multimedia» more  ICMCS 2007»
14 years 1 months ago
A Framework for Modular Signal Processing Systems with High-Performance Requirements
This paper introduces the software framework MMER Lab which allows an effective assembly of modular signal processing systems optimized for memory efficiency and performance. Our...
Lukas Diduch, Ronald Müller, Gerhard Rigoll