314 search results - page 43 / 63 » Generating Path Conditions for Timed Systems |
RE
2001
Springer
14 years 21 hour ago
2001
Springer
A logic model checker can be an effective tool for debugging software applications. A stumbling block can be that model checking tools expect the user to supply a formal statement...
ICALP
1998
Springer
13 years 11 months ago
1998
Springer
Interval Routing Schemes (IRS for short) have been extensively investigated in the past years with special emphasis on shortest paths. Besides their theoretical interest, IRS have...
SASO
2009
IEEE
14 years 2 months ago
2009
IEEE
—In sufficiently large heterogeneous overlays message loss and delays are likely to occur. This has a significant impact on overlay routing, especially on longer paths. The exi...
FPGA
2010
ACM
14 years 4 months ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
WG
1998
Springer
13 years 11 months ago
1998
Springer
In this work we introduce the class of graphs with bounded induced distance of order k, (BID(k) for short). A graph G belongs to BID(k) if the distance between any two nodes in ev...