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» Generating VHDL models from natural language descriptions
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VLSID
2005
IEEE
140views VLSI» more  VLSID 2005»
14 years 7 months ago
Variable Resizing for Area Improvement in Behavioral Synthesis
High level synthesis tools transform an algorithmic description to a register transfer language (RTL) description of the hardware. The algorithm behavior is typically described in...
R. Gopalakrishnan, Rajat Moona
INFORMATICALT
2000
114views more  INFORMATICALT 2000»
13 years 7 months ago
The Language-Centric Program Generator Models: 3L Paradigm
Abstract. In this paper we suggest a three-language (3L) paradigm for building the program generator models. The basis of the paradigm is a relationship model of the specification,...
Vytautas Stuikys, Giedrius Ziberkas, Robertas Dama...
DAC
1997
ACM
13 years 11 months ago
Generation of Software Tools from Processor Descriptions for Hardware/Software Codesign
An experimental set of tools that generate instruction set simulators, assemblers, and disassemblers from a single description was developed to test if retargetable development to...
Mark R. Hartoog, James A. Rowson, Prakash D. Reddy...
INLG
2010
Springer
13 years 5 months ago
Charting the Potential of Description Logic for the Generation of Referring Expressions
The generation of referring expressions (GRE), an important subtask of Natural Language Generation (NLG) is to generate phrases that uniquely identify domain entities. Until recen...
Yuan Ren, Kees van Deemter, Jeff Z. Pan
FDL
2008
IEEE
13 years 9 months ago
RTL Generation of Channel Architecture Templates for a Template-based SoC Design Flow
In this paper, we propose the design methodology for communication channel templates from formal specification to RTL description. In this flow, design and verification start from...
Jinhyun Cho, Soonwoo Choi, Soo Chae