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» Generating high performance pruned FFT implementations
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TIFS
2008
142views more  TIFS 2008»
13 years 8 months ago
An FPGA-Based Network Intrusion Detection Architecture
Abstract--Network intrusion detection systems (NIDSs) monitor network traffic for suspicious activity and alert the system or network administrator. With the onset of gigabit netwo...
Abhishek Das, David Nguyen, Joseph Zambreno, Gokha...
IJRR
2011
174views more  IJRR 2011»
13 years 3 months ago
Bounding on rough terrain with the LittleDog robot
— In this paper we develop an RRT-based motion planner that achieved bounding in simulation with the LittleDog robot over extremely rough terrain. LittleDog is a quadruped robot ...
Alexander C. Shkolnik, Michael Levashov, Ian R. Ma...
LCTRTS
2007
Springer
14 years 2 months ago
Combining source-to-source transformations and processor instruction set extensions for the automated design-space exploration o
Industry’s demand for flexible embedded solutions providing high performance and short time-to-market has led to the development of configurable and extensible processors. The...
Richard Vincent Bennett, Alastair Colin Murray, Bj...
IPCCC
1999
IEEE
14 years 29 days ago
Accurately modeling speculative instruction fetching in trace-driven simulation
Performance evaluation of modern, highly speculative, out-of-order microprocessors and the corresponding production of detailed, valid, accurate results have become serious challe...
R. Bhargava, L. K. John, F. Matus
DLOG
2006
13 years 10 months ago
Tableau Caching for Description Logics with Inverse and Transitive Roles
Abstract. Modern description logic (DL) reasoners are known to be less efficient for DLs with inverse roles. The current loss of performance is largely due to the missing applicabi...
Yu Ding, Volker Haarslev