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IPPS
2006
IEEE
14 years 1 months ago
Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
Michalis D. Galanis, Grigoris Dimitroulakos, Const...
LADC
2005
Springer
14 years 26 days ago
Quantitative Evaluation of Distributed Algorithms Using the Neko Framework: The NekoStat Extension
In this paper we present NekoStat, an extension of the Neko tool. Neko is a Java framework and a communication platform that permits rapid prototyping of distributed applications; ...
Lorenzo Falai, Andrea Bondavalli, Felicita Di Gian...
TCAD
2010
168views more  TCAD 2010»
13 years 2 months ago
An MILP-Based Performance Analysis Technique for Non-Preemptive Multitasking MPSoC
For real-time applications, it is necessary to estimate the worst-case performance early in the design process without actual hardware implementation. While the non-preemptive task...
Hoeseok Yang, Sungchan Kim, Soonhoi Ha
ISCAS
2005
IEEE
113views Hardware» more  ISCAS 2005»
14 years 29 days ago
Effect of traffic localization on energy dissipation in NoC-based interconnect
Multiprocessor system-on-chip (MP-SoC) platforms are emerging as an important trend of SoC design. Scaleable communication-centric interconnect fabrics such as networks-onchip (No...
Partha Pratim Pande, Cristian Grecu, Michael Jones...
AAAI
2006
13 years 8 months ago
The Robot Intelligence Kernel
The Robot Intelligence Kernel (RIK) is a portable, reconfigurable suite of perceptual, behavioral, and cognitive capabilities that can be used across many different platforms, env...
David J. Bruemmer, Douglas A. Few, Miles C. Walton...