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IPPS
2006
IEEE
14 years 3 months ago
Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
Michalis D. Galanis, Grigoris Dimitroulakos, Const...
ISM
2006
IEEE
105views Multimedia» more  ISM 2006»
14 years 3 months ago
MPEG-21 Based Temporal Adaptation of Live H.264 Video
The diversity of devices in both wired and wireless networks via which multimedia contents are desired to be accessed and interacted with has grown significantly. Applications lik...
Razib Iqbal, Shervin Shirmohammadi, Chris Joslin
IWPC
2006
IEEE
14 years 3 months ago
A Metric-Based Heuristic Framework to Detect Object-Oriented Design Flaws
One of the important activities in re-engineering process is detecting design flaws. Such design flaws prevent an efficient maintenance, and further development of a system. Th...
Mazeiar Salehie, Shimin Li, Ladan Tahvildari
VTC
2006
IEEE
14 years 3 months ago
GANS: A Signalling Framework for Dynamic Interworking Between Heterogeneous Networks
— There is a growing trend towards convergence of telecommunication and data networks in order to support a richer set of services and applications. At the same time, increasing ...
Nadeem Akhtar, Rui Campos, Cornelia Kappler, Pekka...
UIST
2006
ACM
14 years 2 months ago
Viz: a visual analysis suite for explaining local search behavior
NP-hard combinatorial optimization problems are common in real life. Due to their intractability, local search algorithms are often used to solve such problems. Since these algori...
Steven Halim, Roland H. C. Yap, Hoong Chuin Lau