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» Graph Rewriting for Hardware Dependent Program Optimizations
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130
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CP
2008
Springer
15 years 4 months ago
A Constraint Programming Approach for Allocation and Scheduling on the CELL Broadband Engine
The Cell BE processor provides both scalable computation power and flexibility, and it is already being adopted for many computational intensive applications like aerospace, defens...
Luca Benini, Michele Lombardi, Michela Milano, Mar...
135
Voted
FPL
2007
Springer
99views Hardware» more  FPL 2007»
15 years 6 months ago
Disjoint Pattern Enumeration for Custom Instructions Identification
Extensible processors allow addition of application-specific custom instructions to the core instruction set architecture. These custom instructions are selected through an analys...
Pan Yu, Tulika Mitra
163
Voted
ISPD
2012
ACM
283views Hardware» more  ISPD 2012»
13 years 10 months ago
Low-power gated bus synthesis for 3d ic via rectilinear shortest-path steiner graph
In this paper, we propose a new approach for gated bus synthesis [16] with minimum wire capacitance per transaction in three-dimensional (3D) ICs. The 3D IC technology connects di...
Chung-Kuan Cheng, Peng Du, Andrew B. Kahng, Shih-H...
156
Voted
WOMPAT
2004
Springer
15 years 8 months ago
Dragon: A Static and Dynamic Tool for OpenMP
A program analysis tool can play an important role in helping users understand and improve OpenMP codes. Dragon is a robust interactive program analysis tool based on the Open64 co...
Oscar Hernandez, Chunhua Liao, Barbara M. Chapman
117
Voted
ICCD
2006
IEEE
117views Hardware» more  ICCD 2006»
15 years 11 months ago
Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses
— The influence of interconnects on processor performance and cost is becoming increasingly pronounced with technology scaling. In this paper, we present a fast compression sche...
Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Maha...