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CODES
2006
IEEE
14 years 1 months ago
Layout aware design of mesh based NoC architectures
Design of System-on-Chip (SoC) with regular mesh based Network-on-Chip (NoC) consists of mapping processing cores to routers, and routing of the traffic traces on the topology suc...
Krishnan Srinivasan, Karam S. Chatha
PASTE
2010
ACM
14 years 12 days ago
Opportunities for concurrent dynamic analysis with explicit inter-core communication
Multicore is now the dominant processor trend, and the number of cores is rapidly increasing. The paradigm shift to multicore forces the redesign of the software stack, which incl...
Jungwoo Ha, Stephen P. Crago
FPL
2005
Springer
122views Hardware» more  FPL 2005»
14 years 25 days ago
FPGA-Aware Garbage Collection in Java
— During codesign of a system, one still runs into the impedance mismatch between the software and hardware worlds. er identifies the different levels of abstraction of hardware...
Philippe Faes, Mark Christiaens, Dries Buytaert, D...
ISSS
1998
IEEE
103views Hardware» more  ISSS 1998»
13 years 11 months ago
False Path Analysis Based on a Hierarchical Control Representation
False path analysis is an activity with applications in a variety of computer science and engineering domains like for instance high-level synthesis, worst case execution time est...
Apostolos A. Kountouris, Christophe Wolinski
ECBS
2003
IEEE
111views Hardware» more  ECBS 2003»
14 years 18 days ago
Multigranular Simulation of Heterogeneous Embedded Systems
Heterogeneous embedded systems, where configurable or application specific hardware devices (FPGAs and ASICs) are used alongside traditional processors, are becoming more and more...
Aditya Agrawal, Ákos Lédeczi