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» Handling variations and uncertainties
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ICCAD
2007
IEEE
118views Hardware» more  ICCAD 2007»
14 years 4 months ago
Timing variation-aware high-level synthesis
—This work proposes a new yield computation technique dedicated to HLS, which is an essential component in timing variationaware HLS research field. The SSTAs used by the curren...
Jongyoon Jung, Taewhan Kim
SAMOS
2009
Springer
14 years 2 months ago
Multiple Description Scalable Coding for Video Transmission over Unreliable Networks
Developing real time multimedia applications for best effort networks such as the Internet requires prohibitions against jitter delay and frame loss. This problem is further compl...
Roya Choupani, Stephan Wong, Mehmet R. Tolun
ECAI
2008
Springer
13 years 9 months ago
Heuristics for Planning with Action Costs Revisited
We introduce a simple variation of the additive heuristic used in the HSP planner that combines the benefits of the original additive heuristic, namely its mathematical formulation...
Emil Keyder, Hector Geffner
FPGA
2008
ACM
174views FPGA» more  FPGA 2008»
13 years 9 months ago
Pattern-based behavior synthesis for FPGA resource reduction
Pattern-based synthesis has drawn wide interest from researchers who tried to utilize the regularity in applications for design optimizations. In this paper we present a general p...
Jason Cong, Wei Jiang
CVPR
2007
IEEE
14 years 9 months ago
Bilattice-based Logical Reasoning for Human Detection
The capacity to robustly detect humans in video is a critical component of automated visual surveillance systems. This paper describes a bilattice based logical reasoning approach...
Vinay D. Shet, Jan Neumann, Visvanathan Ramesh, La...