Sciweavers

112 search results - page 9 / 23
» Hardware Acceleration of Matrix Multiplication on a Xilinx F...
Sort
View
ASAP
2008
IEEE
146views Hardware» more  ASAP 2008»
14 years 2 months ago
A multi-FPGA application-specific architecture for accelerating a floating point Fourier Integral Operator
Many complex systems require the use of floating point arithmetic that is exceedingly time consuming to perform on personal computers. However, floating point operators are also h...
Jason Lee, Lesley Shannon, Matthew J. Yedlin, Gary...
IJNSEC
2010
247views more  IJNSEC 2010»
13 years 2 months ago
Hardware Implementation of Efficient Modified Karatsuba Multiplier Used in Elliptic Curves
The efficiency of the core Galois field arithmetic improves the performance of elliptic curve based public key cryptosystem implementation. This paper describes the design and imp...
Sameh M. Shohdy, Ashraf El-Sisi, Nabil A. Ismail
ERSA
2010
159views Hardware» more  ERSA 2010»
13 years 5 months ago
Acceleration of FPGA Fault Injection Through Multi-Bit Testing
SRAM-based FPGA devices are an attractive option for data processing on space-based platforms, due to high computational capabilities and a lower power envelope than traditional pr...
Grzegorz Cieslewski, Alan D. George, Adam Jacobs
INTEGRATION
2007
98views more  INTEGRATION 2007»
13 years 7 months ago
Hashchip: A shared-resource multi-hash function processor architecture on FPGA
The ubiquitous presence of mobile devices and the demand for better performance and efficiency have motivated research into embedded implementations of cryptography algorithms. I...
T. S. Ganesh, Michael T. Frederick, T. S. B. Sudar...
ENC
2004
IEEE
13 years 11 months ago
On the Hardware Design of an Elliptic Curve Cryptosystem
We present a hardware architecture for an Elliptic Curve Cryptography System performing the three basic cryptographic schemes: DH key generation, encryption and digital signature....
Miguel Morales-Sandoval, Claudia Feregrino Uribe