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SOSP
2009
ACM
14 years 6 months ago
ODR: output-deterministic replay for multicore debugging
Reproducing bugs is hard. Deterministic replay systems address this problem by providing a high-fidelity replica of an original program run that can be repeatedly executed to zer...
Gautam Altekar, Ion Stoica
FASE
2009
Springer
14 years 4 months ago
HAVE: Detecting Atomicity Violations via Integrated Dynamic and Static Analysis
Abstract. The reality of multi-core hardware has made concurrent programs pervasive. Unfortunately, writing correct concurrent programs is difficult. Atomicity violation, which is ...
Qichang Chen, Liqiang Wang, Zijiang Yang, Scott D....
IEEEPACT
2007
IEEE
14 years 4 months ago
Call-chain Software Instruction Prefetching in J2EE Server Applications
We present a detailed characterization of instruction cache performance for IBM’s J2EE-enabled web server, WebSphere Application Server (WAS). When running two J2EE benchmarks o...
Priya Nagpurkar, Harold W. Cain, Mauricio J. Serra...
CAV
2007
Springer
121views Hardware» more  CAV 2007»
14 years 3 months ago
Algorithms for Interface Synthesis
Abstract. A temporal interface for a software component is a finite automaton that specifies the legal sequences of calls to functions that are provided by the component. We comp...
Dirk Beyer, Thomas A. Henzinger, Vasu Singh
ASPDAC
2005
ACM
98views Hardware» more  ASPDAC 2005»
14 years 3 months ago
Bitwidth-aware scheduling and binding in high-level synthesis
- Many high-level description languages, such as C/C++ or Java, lack the capability to specify the bitwidth information for variables and operations. Synthesis from these specifica...
Jason Cong, Yiping Fan, Guoling Han, Yizhou Lin, J...