951 search results - page 24 / 191 » Hardware design experiences in ZebraNet |
IPPS
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—Widespread emergence of multicore processors will spur development of parallel applications, exposing programmers to degrees of hardware concurrency hitherto unavailable...
DAC
2000
ACM
14 years 8 months ago
2000
ACM
In this paper, we propose a technique to implement communication protocols as hardware circuits using a model of concurrent EFSMs with multi-way synchronization. Since use of mult...
GLOBECOM
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract−Several high performance LDPC codes have paritycheck matrices composed of permutation submatrices. We design a parallel-serial architecture to map the decoder of any str...
SPAA
2010
ACM
14 years 13 days ago
2010
ACM
We explore the potential of hardware transactional memory (HTM) to improve concurrent algorithms. We illustrate a number of use cases in which HTM enables significantly simpler c...
VSTTE
2005
Springer
14 years 1 months ago
2005
Springer
The interplay back and forth between software model checking and hardware model checking has been fruitful for both. Originally intended for the analysis of concurrent software, mo...