951 search results - page 26 / 191 » Hardware design experiences in ZebraNet |
CODES
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper presents a hw/sw codesign methodology based on BORPH, an operating system designed for FPGA-based reconfigurable computers (RC's). By providing native kernel suppo...
ASYNC
1999
IEEE
13 years 12 months ago
1999
IEEE
The counterflow pipeline architecture [12] consists of two interacting pipelines in which data items flow in opposite directions. Interactions occur between two items when they me...
DPHOTO
2009
13 years 5 months ago
2009
Most digital cameras employ a spatial subsampling process, implemented as a color filter array (CFA), to capture color images. The choice of CFA patterns has a great impact on the...
FPL
2004
Springer
13 years 11 months ago
2004
Springer
In this paper, we develop a unified theory in analyzing optimal switch box design problems, particularly for the unsolved irregular cases, where different pin counts are allowed on...
ATS
2001
IEEE
13 years 11 months ago
2001
IEEE
Test access is a major problem for core-based systemon-chip (SOC) designs. Since cores in an SOC are not directly accessible via chip inputs and outputs, special access mechanisms...