Sciweavers

734 search results - page 85 / 147
» Hardware support for code integrity in embedded processors
Sort
View
IWOMP
2007
Springer
14 years 1 months ago
Supporting OpenMP on Cell
The Cell processor is a heterogeneous multi-core processor with one Power Processing Engine (PPE) core and eight Synergistic Processing Engine (SPE) cores. Each SPE has a directly...
Kevin O'Brien, Kathryn M. O'Brien, Zehra Sura, Ton...
VLSID
1999
IEEE
99views VLSI» more  VLSID 1999»
13 years 12 months ago
Array Index Allocation under Register Constraints in DSP Programs
Abstract Code optimization for digital signal processors DSPs has been identi ed as an important new topic in system-level design of embedded systems. Both DSP processors and algor...
Anupam Basu, Rainer Leupers, Peter Marwedel
SP
2007
IEEE
113views Security Privacy» more  SP 2007»
14 years 1 months ago
Minimal TCB Code Execution
TCB Code Execution (Extended Abstract)∗ Jonathan M. McCune, Bryan Parno, Adrian Perrig, Michael K. Reiter, and Arvind Seshadri Carnegie Mellon University We propose an architect...
Jonathan M. McCune, Bryan Parno, Adrian Perrig, Mi...
ASPDAC
2008
ACM
103views Hardware» more  ASPDAC 2008»
13 years 9 months ago
Reliability-aware design for nanometer-scale devices
Continuous transistor scaling due to improvements in CMOS devices and manufacturing technologies is increasing processor power densities and temperatures; thus, creating challenges...
David Atienza, Giovanni De Micheli, Luca Benini, J...
PC
2007
343views Management» more  PC 2007»
13 years 7 months ago
Runtime scheduling of dynamic parallelism on accelerator-based multi-core systems
We explore runtime mechanisms and policies for scheduling dynamic multi-grain parallelism on heterogeneous multi-core processors. Heterogeneous multi-core processors integrate con...
Filip Blagojevic, Dimitrios S. Nikolopoulos, Alexa...