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» Heterogeneous behavioral hierarchy for system level designs
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ISVLSI
2006
IEEE
89views VLSI» more  ISVLSI 2006»
14 years 2 months ago
System Exploration of SystemC Designs
Due to increasing design complexity new methodologies for system modeling have been established in VLSI CAD. The SystemC methodology gains a significant reduction of design cycle...
Christian Genz, Rolf Drechsler
MEMOCODE
2010
IEEE
13 years 6 months ago
Proving transaction and system-level properties of untimed SystemC TLM designs
Electronic System Level (ESL) design manages the complexity of todays systems by using abstract models. In this context Transaction Level Modeling (TLM) is state-of-theart for desc...
Daniel Große, Hoang M. Le, Rolf Drechsler
ASPDAC
2012
ACM
253views Hardware» more  ASPDAC 2012»
12 years 4 months ago
An integrated and automated memory optimization flow for FPGA behavioral synthesis
Behavioral synthesis tools have made significant progress in compiling high-level programs into register-transfer level (RTL) specifications. But manually rewriting code is still ...
Yuxin Wang, Peng Zhang, Xu Cheng, Jason Cong
KBSE
2005
IEEE
14 years 2 months ago
Designing and implementing a family of intrusion detection systems
Intrusion detection systems are distributed applications that analyze the events in a networked system to identify malicious behavior. The analysis is performed using a number of ...
Richard A. Kemmerer
CONCUR
1999
Springer
14 years 1 months ago
Statecharts Via Process Algebra
Statecharts is a visual language for specifying the behavior of reactive systems. The language extends nite-state machines with concepts of hierarchy, concurrency, and priority. De...
Gerald Lüttgen, Michael von der Beeck, Rance ...