901 search results - page 22 / 181 » Hiding Communication Latency in Data Parallel Applications |
HPCA
1997
IEEE
13 years 12 months ago
1997
IEEE
Processors with write-through caches typically require a write buffer to hide the write latency to the next level of memory hierarchy and to reduce write traffic. A write buffer ...
MICRO
2010
IEEE
13 years 6 months ago
2010
IEEE
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
WWW
2005
ACM
14 years 8 months ago
2005
ACM
We present GlobeDB, a system for hosting Web applications that performs autonomic replication of application data. GlobeDB offers data-intensive Web applications the benefits of l...
ICS
1999
Tsinghua U.
14 years 1 days ago
1999
Tsinghua U.
The Virtual Interface (VI) Architecture provides protected userlevel communication with high delivered bandwidth and low permessage latency, particularly for small messages. The V...
ICS
1998
Tsinghua U.
13 years 12 months ago
1998
Tsinghua U.
The goal of High Performance Fortran (HPF) is to "address the problems of writing data parallel programs where the distribution of data affects performance", providing t...