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» Hiding Communication Latency in Data Parallel Applications
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ISCA
2012
IEEE
280views Hardware» more  ISCA 2012»
11 years 10 months ago
A case for random shortcut topologies for HPC interconnects
—As the scales of parallel applications and platforms increase the negative impact of communication latencies on performance becomes large. Fortunately, modern High Performance C...
Michihiro Koibuchi, Hiroki Matsutani, Hideharu Ama...
CANPC
1999
Springer
14 years 10 days ago
Implementing Application-Specific Cache-Coherence Protocols in Configurable Hardware
Streamlining communication is key to achieving good performance in shared-memory parallel programs. While full hardware support for cache coherence generally offers the best perfo...
David Brooks, Margaret Martonosi
MIDDLEWARE
2005
Springer
14 years 1 months ago
Integrated support for handoff management and context awareness in heterogeneous wireless networks
The overwhelming success of mobile devices and wireless communications is stressing the need for the development of mobility-aware services. Device mobility requires services adap...
Paolo Bellavista, Marcello Cinque, Domenico Cotron...
IEEEPACT
1998
IEEE
14 years 9 days ago
Athapascan-1: On-Line Building Data Flow Graph in a Parallel Language
In order to achieve practical efficient execution on a parallel architecture, a knowledge of the data dependencies related to the application appears as the key point for building...
François Galilée, Jean-Louis Roch, G...
HPCA
1998
IEEE
14 years 9 days ago
The Impact of Data Transfer and Buffering Alternatives on Network Interface Design
The explosive growth in the performance of microprocessors and networks has created a new opportunity to reduce the latency of fine-grain communication. Microprocessor clock speed...
Shubhendu S. Mukherjee, Mark D. Hill