17 search results - page 1 / 4 » Hiding Memory Latency using Dynamic Scheduling in Shared-Mem... |
ISCA
1992
IEEE
14 years 2 months ago
1992
IEEE
EUROPAR
2009
Springer
14 years 5 months ago
2009
Springer
Abstract. We consider approaches that allow task migration for scheduling recurrent directed-acyclic-graph (DAG) tasks on symmetric, shared-memory multiprocessors (SMPs) in order t...
ICPP
2007
IEEE
14 years 5 months ago
2007
IEEE
Ever-increasing memory footprint of applications and increasing mainstream popularity of shared memory parallel computing motivate us to explore memory compression potential in di...
ASPLOS
1991
ACM
14 years 2 months ago
1991
ACM
The memory consistency model supported by a multiprocessor architecture determines the amount of buffering and pipelining that may be used to hide or reduce the latency of memory ...
HPCA
2000
IEEE
14 years 3 months ago
2000
IEEE
Abstract—Sharing patterns in shared-memory multiprocessors are the key to performance: uniprocessor latencytolerating techniques such as out-of-order execution and non-blocking c...