238 search results - page 8 / 48 » Hierarchical Interconnect Circuit Models |
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
Abstract— The analysis of effects induced by interconnects become increasingly important as the scale of process technologies steadily shrinks. While most analyses focus on the t...
PATMOS
2005
Springer
14 years 1 months ago
2005
Springer
Early circuit performance estimation and easy-to-apply methods for minimum-delay gate sizing are needed, in order to enhance circuit’s performance and to increase designers’ pr...
GLVLSI
2003
IEEE
14 years 27 days ago
2003
IEEE
—Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. A model of the effectiv...
BMAS
2000
IEEE
14 years 22 hour ago
2000
IEEE
In this paper the problem of accommodating particular analog system models, with emphasis on interconnection's representation, with discrete event simulators, and particularl...
EURODAC
1994
IEEE
13 years 11 months ago
1994
IEEE
In performance-driven interconnect design, delay estimators are used to determine both the topology and the layout of good routing trees. We address the class of moment-matching, ...