251 search results - page 16 / 51 » Hierarchical Modeling and Simulation of Large Analog Circuit... |
DAC
2007
ACM
14 years 8 months ago
2007
ACM
In this paper we propose a novel parameterized macromodeling technique for analog circuits. Unlike traditional macromodels that are only extracted for a small variation space, our...
DATE
2003
IEEE
14 years 25 days ago
2003
IEEE
† Noise performance is a critical analog and RF circuit design constraint, and can impact the selection of the IC system-level architecture. It is therefore imperative that some ...
ASPDAC
2005
ACM
13 years 9 months ago
2005
ACM
— We develop a realizable circuit reduction to generate the interconnect macro-model for parasitic estimation in wideband applications. The inductance is represented by VPEC (vec...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
A new approach in hierarchical optimisation is presented which is capable of optimising both the performance and yield of an analogue design. Performance and yield trade offs are ...
ASPDAC
1999
ACM
13 years 12 months ago
1999
ACM
A method is introduced for model order reduction of large circuits extracted from layout. The algorithm, which is based on balanced realization, can be used for reducing the order ...