251 search results - page 25 / 51 » Hierarchical Modeling and Simulation of Large Analog Circuit... |
ICCAD
1995
IEEE
13 years 11 months ago
1995
IEEE
This paper presents a linear time algorithm to reduce a large RC interconnect network into subnetworks which are approximated with lower order equivalent RC circuits. The number o...
WCE
2007
13 years 8 months ago
2007
—Clock jitter and its effects on signal-to-noise ratio (SNR) were widely investigated in the published literatures. However, most of the issues mainly focused on white-Gaussian-n...
GLVLSI
2003
IEEE
14 years 26 days ago
2003
IEEE
Modeling on-chip inductive effects for interconnects of multigigahertz microprocessors remains challenging. SPICE simulation of these effects is very slow because of the large num...
ET
2000
13 years 7 months ago
2000
The paper presents a novel hierarchical approach to test pattern generation for sequential circuits based on an input model of mixed-level decision diagrams. A method that handles,...
RT
2000
Springer
13 years 11 months ago
2000
Springer
We present the concept of hierarchical instantiation for radiosity. This new method enables an efficient, yet accurate determination of the illumination in very large scenes, wher...