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TVLSI
2002
93views more  TVLSI 2002»
13 years 7 months ago
Simultaneous switching noise in on-chip CMOS power distribution networks
Simultaneous switching noise (SSN) has become an important issue in the design of the internal on-chip power distribution networks in current very large scale integration/ultra lar...
Kevin T. Tang, Eby G. Friedman
PADS
1996
ACM
13 years 11 months ago
Design of High Level Modelling / High Performance Simulation Environments
Advances in massively parallel platforms are increasing the prospects for high performance discrete event simulation. Still the di culty in parallel programming persists and there...
Bernard P. Zeigler, Doohwan Kim
DAC
2000
ACM
13 years 12 months ago
Fast power grid simulation
The decrease in feature size and added chip functionality in large sub-micron integrated circuits demand larger grids for power distribution. Since power grids are performance lim...
Sani R. Nassif, Joseph N. Kozhaya
ASPDAC
2010
ACM
165views Hardware» more  ASPDAC 2010»
13 years 5 months ago
Dynamic power estimation for deep submicron circuits with process variation
- Dynamic power consumption in CMOS circuits is usually estimated based on the number of signal transitions. However, when considering glitches, this is not accurate because narrow...
Quang Dinh, Deming Chen, Martin D. F. Wong
TACAS
1998
Springer
98views Algorithms» more  TACAS 1998»
13 years 11 months ago
Efficient Modeling of Memory Arrays in Symbolic Ternary Simulation
This paper enables symbolic ternary simulation of systems with large embedded memories. Each memory array is replaced with a behavioral model, where the number of symbolic variable...
Miroslav N. Velev, Randal E. Bryant