Sciweavers

319 search results - page 28 / 64
» Hierarchical Simulation of a Multiprocessor Architecture
Sort
View
INFOCOM
2003
IEEE
14 years 26 days ago
S-MIP: A Seamless Handoff Architecture for Mobile IP
—As the number of Mobile IP (MIP) [2] users grow, so will the demand for delay sensitive real-time applications, such as audio streaming, that require seamless handoff, namely, a...
Robert Hsieh, Zhe Guang Zhou, Aruna Seneviratne
RT
2000
Springer
13 years 11 months ago
Hierarchical Instantiation for Radiosity
We present the concept of hierarchical instantiation for radiosity. This new method enables an efficient, yet accurate determination of the illumination in very large scenes, wher...
Cyril Soler, François X. Sillion
SIGGRAPH
2000
ACM
13 years 12 months ago
Pomegranate: a fully scalable graphics architecture
Pomegranate is a parallel hardware architecture for polygon rendering that provides scalable input bandwidth, triangle rate, pixel rate, texture memory and display bandwidth while...
Matthew Eldridge, Homan Igehy, Pat Hanrahan
ESTIMEDIA
2004
Springer
14 years 1 months ago
A queuing-theoretic performance model for context-flow system-on-chip platforms
Abstract—Few analytical performance models that relate performance figure of merit to architectural design decisions are reported in recent studies of network-on-chip, which pre...
Rami Beidas, Jianwen Zhu
EH
2000
IEEE
81views Hardware» more  EH 2000»
14 years 12 hour ago
Toward Self-Repairing and Self-Replicating Hardware: The Embryonics Approach
The growth and operation of all living beings are directed by the interpretation, in each of their cells, of a chemical program, the DNA string or genome. This process is the sour...
Daniel Mange, Moshe Sipper, André Stauffer,...