319 search results - page 53 / 64 » Hierarchical Simulation of a Multiprocessor Architecture |
SLIP
2009
ACM
14 years 2 months ago
2009
ACM
The present paper is part of a larger effort to redesign, from the ground up, the best possible interconnect topologies for switchless multiprocessor computer systems. We focus he...
ITNG
2008
IEEE
14 years 1 months ago
2008
IEEE
This paper presents several parallel FFT algorithms with different degree of communication overhead for multiprocessors in Network-on-Chip(NoC) environment. Three different method...
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
Multiprocessor system-on-chip (MP-SoC) platforms are emerging as an important trend of SoC design. Scaleable communication-centric interconnect fabrics such as networks-onchip (No...
IPPS
2000
IEEE
13 years 12 months ago
2000
IEEE
The Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus) is a low-latency, high-bandwidth interconnection network which directly links arbitrary pairs of processor nodes wit...
ICPP
1998
IEEE
13 years 11 months ago
1998
IEEE
Exploiting locality at run-time is a complementary approach to a compiler approach for those applications with dynamic memory access patterns. This paper proposes a memory-layout ...