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2007
13 years 10 months ago
Karma: Know-It-All Replacement for a Multilevel Cache
Multilevel caching, common in many storage configurations, introduces new challenges to traditional cache management: data must be kept in the appropriate cache and replication a...
Gala Yadgar, Michael Factor, Assaf Schuster
CIARP
2007
Springer
13 years 10 months ago
Morphological Distinguished Regions
Abstract. Distinguished regions can be detected with high repeatability in different images of the same scene. Two definitions of distinguished regions of an image in a mathemati...
Allan Hanbury
VLSID
2008
IEEE
150views VLSI» more  VLSID 2008»
14 years 9 months ago
PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors
Simultaneous Multi-Threading (SMT) processors are becoming popular because they exploit both instruction-level and threadlevel parallelism by issuing instructions from different t...
Deepa Kannan, Aseem Gupta, Aviral Shrivastava, Nik...
HPCC
2009
Springer
14 years 1 months ago
On Instruction-Level Method for Reducing Cache Penalties in Embedded VLIW Processors
Usual cache optimisation techniques for high performance computing are difficult to apply in embedded VLIW applications. First, embedded applications are not always well structur...
Samir Ammenouche, Sid Ahmed Ali Touati, William Ja...
ISCA
2007
IEEE
130views Hardware» more  ISCA 2007»
13 years 8 months ago
Non-Inclusion Property in Multi-Level Caches Revisited
The center of gravity of computer architecture is moving toward memory systems. Barring breakthrough microarchitectural techniques to move processor performance to higher levels, ...
Mohamed M. Zahran, Kursad Albayraktaroglu, Manoj F...