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ISCAPDCS
2004
13 years 9 months ago
One-Level Cache Memory Design for Scalable SMT Architectures
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past de...
Muhamed F. Mudawar, John R. Wani
ISCAPDCS
2007
13 years 9 months ago
Architectural requirements of parallel computational biology applications with explicit instruction level parallelism
—The tremendous growth in the information culture, efficient digital searches are needed to extract and identify information from huge data. The notion that evolution in silicon ...
Naeem Zafar Azeemi
IPPS
1999
IEEE
14 years 4 days ago
Process Networks as a High-Level Notation for Metacomputing
Abstract. Our work involves the development of a prototype Geographical Information System GIS as an example of the use of process networks as a well-de ned high-level semantic mod...
Darren Webb, Andrew L. Wendelborn, Kevin Maciunas
OOPSLA
1998
Springer
14 years 2 days ago
Visualizing Dynamic Software System Information Through High-Level Models
Dynamic information collected as a software system executes can help software engineers perform some tasks on a system more effectively. To interpret the sizable amount of data ge...
Robert J. Walker, Gail C. Murphy, Bjørn N. ...
IPPS
2000
IEEE
14 years 7 days ago
Controlling Distributed Shared Memory Consistency from High Level Programming Languages
One of the keys for the success of parallel processing is the availability of high-level programming languages for on-the-shelf parallel architectures. Using explicit message passi...
Yvon Jégou