624 search results - page 120 / 125 » High Performance Matrix Multiplication on Many Cores |
ISCA
2009
IEEE
14 years 2 months ago
2009
IEEE
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
INFOCOM
2006
IEEE
14 years 1 months ago
2006
IEEE
— Efficient and scalable live-streaming overlay construction has become a hot topic recently. In order to improve the performance metrics, such as startup delay, source-to-end de...
CONEXT
2005
ACM
13 years 9 months ago
2005
ACM
The high bandwidth and low latency of the modern internet has made possible the deployment of distributed computing platforms. The XenoServer platform provides a distributed compu...
CJ
2006
13 years 7 months ago
2006
Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction ...
Publication
Ease of deployment, wireless connectivity and ubiquitous mobile on-the-go computing has made the IEEE 802.11 the most widely deployed Wireless Local Area Network (WLAN) sta...