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CASES
2008
ACM
13 years 11 months ago
Efficiency and scalability of barrier synchronization on NoC based many-core architectures
Interconnects based on Networks-on-Chip are an appealing solution to address future microprocessor designs where, very likely, hundreds of cores will be connected on a single chip...
Oreste Villa, Gianluca Palermo, Cristina Silvano
WSC
2008
13 years 12 months ago
High speed semiconductor fab simulation for large, medium and small lot sizes
This paper describes an analysis performed to assess the fidelity, scalability, and performance of the Sage
Peter C. Bosch, Robert L. Wright
EUROPAR
2006
Springer
14 years 1 months ago
PAM-SoC: A Toolchain for Predicting MPSoC Performance
In the past, research on Multiprocessor Systems-on-Chip (MPSoC) has focused mainly on increasing the available processing power on a chip, while less effort was put into specific s...
Ana Lucia Varbanescu, Henk J. Sips, Arjan J. C. va...
DTJ
1998
171views more  DTJ 1998»
13 years 9 months ago
Measurement and Analysis of C and C++ Performance
ir increasing use of abstraction, modularity, delayed binding, polymorphism, and source reuse, especially when these attributes are used in combination. Modern processor architectu...
Hemant G. Rotithor, Kevin W. Harris, Mark W. Davis
FLAIRS
2008
13 years 12 months ago
A Backward Adjusting Strategy and Optimization of the C4.5 Parameters to Improve C4.5's Performance
In machine learning, decision trees are employed extensively in solving classification problems. In order to design a decision tree classifier two main phases are employed. The fi...
Jason R. Beck, Maria Garcia, Mingyu Zhong, Michael...