733 search results - page 56 / 147 » High performance in tree-based parallel architectures |
ASPLOS
1992
ACM
14 years 1 months ago
1992
ACM
The foremost goal of superscalar processor design is to increase performance through the exploitation of instruction-level parallelism (ILP). Previous studies have shown that spec...
EH
2004
IEEE
14 years 20 days ago
2004
IEEE
The use of Application Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to ...
WMPI
2004
ACM
14 years 2 months ago
2004
ACM
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
IPPS
2002
IEEE
14 years 1 months ago
2002
IEEE
Distributed Computing, the exploitation of idle cycles on pervasive desktop PC systems offers the opportunity to increase the available computing power by orders of magnitude (10x...
FPL
2009
Springer
14 years 1 months ago
2009
Springer
Networks-on-Chips (NoCs) are an emerging communication topology paradigm in single chip VLSI design, enhancing parallelism and system scalability. Processing units (PUs) connect t...