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CCS
2011
ACM
12 years 8 months ago
MIDeA: a multi-parallel intrusion detection architecture
Network intrusion detection systems are faced with the challenge of identifying diverse attacks, in extremely high speed networks. For this reason, they must operate at multi-Giga...
Giorgos Vasiliadis, Michalis Polychronakis, Sotiri...
FPL
2006
Springer
135views Hardware» more  FPL 2006»
14 years 16 days ago
FPGA Design Considerations in the Implementation of a Fixed-Throughput Sphere Decoder for MIMO Systems
A field-programmable gate array (FPGA) implementation of a new detection algorithm for uncoded multiple inputmultiple output (MIMO) systems based on the complex version of the sph...
Luis G. Barbero, John S. Thompson
TSP
2011
144views more  TSP 2011»
13 years 3 months ago
On Decentralized Detection With Partial Information Sharing Among Sensors
—We study a decentralized detection architecture in which each of a set of sensors transmits a highly compressed summary of its observations (a binary message) to a fusion center...
O. Patrick Kreidl, John N. Tsitsiklis, Spyros I. Z...
ASAP
2005
IEEE
169views Hardware» more  ASAP 2005»
14 years 2 months ago
Alleviating the Data Memory Bandwidth Bottleneck in Coarse-Grained Reconfigurable Arrays
It is widely known that parallel operation execution in multiprocessor systems generates a respective increase in memory accesses. Since the memory and bus subsystems provide a li...
Grigoris Dimitroulakos, Michalis D. Galanis, Costa...
ASPDAC
2006
ACM
143views Hardware» more  ASPDAC 2006»
14 years 2 months ago
Constraint-driven bus matrix synthesis for MPSoC
– Modern multi-processor system-on-chip (MPSoC) designs have high bandwidth constraints which must be satisfied by the underlying communication architecture. Bus matrix based com...
Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdha...