733 search results - page 96 / 147 » High performance in tree-based parallel architectures |
IEEEPACT
2005
IEEE
14 years 2 months ago
2005
IEEE
Global address space languages like UPC exhibit high performance and portability on a broad class of shared and distributed memory parallel architectures. The most scalable applic...
CGO
2007
IEEE
14 years 3 months ago
2007
IEEE
The increasing complexity of hardware features for recent processors makes high performance code generation very challenging. In particular, several optimization targets have to b...
FCCM
2011
IEEE
13 years 17 days ago
2011
IEEE
— This paper describes an architecture and FPGA synthesis toolchain for building specialized, energy-saving coprocessors called Irregular Code Energy Reducers (ICERs) for a wide ...
PPL
2002
13 years 8 months ago
2002
Virtual Interface Architecture(VIA) is a light-weight protocol for protected user-level zero-copy communication. In spite of the promised high performance of VIA, previous MPI imp...
CLUSTER
2006
IEEE
14 years 2 months ago
2006
IEEE
IP routers are now increasingly expected to do more than just traditional packet forwarding – they must be extensible as well as scalable. It is a challenge to design a router a...