1024 search results - page 30 / 205 » High-Level Execution Time Analysis |
123
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RTSS
2003
IEEE
15 years 8 months ago
2003
IEEE
This paper presents a quantification of the timing effects that advanced processor features like data and instruction cache, pipelines, branch prediction units and out-oforder ex...
121
Voted
SIGCOMM
1997
ACM
15 years 6 months ago
1997
ACM
Abstract—This paper examines the network interdomain routing information exchanged between backbone service providers at the major U.S. public Internet exchange points. Internet ...
117
Voted
RTAS
2008
IEEE
15 years 9 months ago
2008
IEEE
This paper formulates and illustrates the integration of resource safety verification into a design methodology for development of verified and robust real-time embedded systems. ...
127
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ENTCS
2002
15 years 2 months ago
2002
This paper extends the well-known technique of slicing to synchronous reactive programs. Synchronous languages exemplified by Esterel, Lustre, Signal and Argos, novel model of exe...
182
Voted
ISORC
2011
IEEE
14 years 6 months ago
2011
IEEE
—Static cache analysis for data allocated on the heap is practically impossible for standard data caches. We propose a distinct object cache for heap allocated data. The cache is...