Verification conditions (VCs) are logical formulae whose validity implies the correctness of a program with respect to a specification. The technique of checking software properti...
: This paper presents the design of a neurocontroller for a turbogenerator that augments/replaces the conventional Automatic Voltage Regulator (AVR) and the turbine governor. The n...
Ganesh K. Venayagamoorthy, Ronald G. Harley, Donal...
We introduce an axiomatic definition of a conditional convex risk mapping and we derive its properties. In particular, we prove a representation theorem for conditional risk mappi...
Equality constraints (unification constraints) have widespread use in program analysis, most notably in static polymorphic type systems. Conditional equality constraints extend eq...
Call graphs are commonly used as input for automatic clustering algorithms, the goal of which is to extract the high level structure of the program under study. Determining the ca...
Derek Rayside, Steve Reuss, Erik Hedges, Kostas Ko...